A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption
| Main Authors: | Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati |
|---|---|
| Format: | Article Journal |
| Bahasa: | eng |
| Terbitan: |
, 2008
|
| Online Access: |
https://zenodo.org/record/1334317 |
| ctrlnum |
1334317 |
|---|---|
| fullrecord |
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<dc schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><creator>Arash Azizi Mazreah</creator><creator>Mohammad T. Manzuri Shalmani</creator><creator>Hamid Barati</creator><creator>Ali Barati</creator><date>2008-03-25</date><description>This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.</description><identifier>https://zenodo.org/record/1334317</identifier><identifier>10.5281/zenodo.1334317</identifier><identifier>oai:zenodo.org:1334317</identifier><language>eng</language><relation>doi:10.5281/zenodo.1334316</relation><rights>info:eu-repo/semantics/openAccess</rights><rights>https://creativecommons.org/licenses/by/4.0/legalcode</rights><source>International Journal of Electrical, Electronic and Communication Sciences 1.0(3)</source><title>A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption</title><type>Journal:Article</type><type>Journal:Article</type><recordID>1334317</recordID></dc>
|
| language |
eng |
| format |
Journal:Article Journal Journal:Journal |
| author |
Arash Azizi Mazreah Mohammad T. Manzuri Shalmani Hamid Barati Ali Barati |
| title |
A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption |
| publishDate |
2008 |
| url |
https://zenodo.org/record/1334317 |
| contents |
This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper. |
| id |
IOS16997.1334317 |
| institution |
ZAIN Publications |
| institution_id |
7213 |
| institution_type |
library:special library |
| library |
Cognizance Journal of Multidisciplinary Studies |
| library_id |
5267 |
| collection |
Cognizance Journal of Multidisciplinary Studies |
| repository_id |
16997 |
| subject_area |
Multidisciplinary |
| city |
Stockholm |
| province |
INTERNASIONAL |
| shared_to_ipusnas_str |
1 |
| repoId |
IOS16997 |
| first_indexed |
2022-06-06T06:07:41Z |
| last_indexed |
2022-06-06T06:07:41Z |
| recordtype |
dc |
| _version_ |
1734907579736260608 |
| score |
17.611225 |