IMPLEMENTASI KRIPTOGRAFI AES-128 PADA FIELD PROGRAMMABLE GATE ARRAY (FPGA) (Implementation of AES-128 Cryptography using Field Programmable Gate Arrays (FPGA)
| Main Author: | YUSRAN MASHAMI |
|---|---|
| Format: | Bachelors |
| Terbitan: |
Universitas Telkom
, 2006
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| Subjects: | |
| Online Access: |
https://openlibrary.telkomuniversity.ac.id/pustaka/90477/implementasi-kriptografi-aes-128-pada-field-programmable-gate-array-fpga-implementation-of-aes-128-cryptography-using-field-programmable-gate-arrays-fpga-.html |
Daftar Isi:
- ABSTRAKSI: Pada tugas akhir ini diimplementasikan algoritma kriptografi simetris AES (Advanced Encryption Standard) dengan panjang kunci 128 bit dimana proses enkripsi dan dekripsi dilakukan dalam satu chip/core yaitu pada Xilinx XC2S300E PQ208-6. Mode operasi menggunakan ECB (Electronic Code Book). Pemodelan rancangan menggunakan bahasa VHDL (Very High Speed Integrated Circuit Hardware Language). Simulasi dengan menggunakan ModelSim SE 6.0 berdasarkan KAT (Known Answer Test) dari pembuat algoritma, kemudian disintesis dan diimplementasikan menggunakan Xilinx ISE 7.1.03i, serta diverifikasi menggunakan Chipscope Pro 7.1.03i.<br>Hasil implementasi menunjukkan bahwa implementasi kriptografi AES-128 ini mampu bekerja pada frekuensi maksimum 28.771 MHz dengan throughput sebesar 167,395 Mbps pada frekuensi tersebut dan area yang dibutuhkan sebanyak 35.460 gate ekivalen.AES-128, Enkripsi, Dekripsi, ECB, VHDL, KAT, Throughput, Area.Kata Kunci : AES-128, Enkripsi, Dekripsi, ECB, VHDL, KAT, Throughput, Area.ABSTRACT: This final project presents an implementation of symmetric cryptography algorithm AES (Advanced Encryption Standard) that use key length of 128 bits which can processes either encryption or decryption in one core (Xilinx XC2300E PQ208-6). The implementation used ECB (Electronic Code Book) operation mode. The implementation design is modeled in VHDL (Very High Speed Integrated Circuit Hardware Language), then simulated using ModelSim SE 6.0 based on KAT (Known Answer Test) from the AES creator. It is also sinthesized and implemented using Xilinx ISE 7.1.03i, then verified on chip using Chipscope Pro 7.1.03i.<br>The results of implementation show that the AES-128 core is available on maximum frequency 28.771 MHz with throughput 167,395 Mbps on that frequency and the circuit area needed is 35.460 equivalent gates.Keyword: AES-128, ECB, VHDL, Encryption, Decryption, KAT, Throughput, Area.